HIGH SPEED ENERGY EFFICIENT STATIC SEGMENT ADDER FOR APPROXIMATE
HIGH SPEED ENERGY EFFICIENT STATIC SEGMENT ADDER FOR APPROXIMATE COMPUTING APPLICATIONSAbstract: In general digital data computing design needs to achieve high performance with required accuracy range. The high performance involves low power, area efficiency and high speed. This paper proposes a design of High speed energy efficient static segment adder (SSA) which improves the overall performance based on approximation. Static segmentation includes both accurate and inaccurate part. By using static segmentation the approximate computation is done. Approximate computing is a computation which returns a possibly inaccurate result rather than a guarantee accurate result. For example: Image enhancement operation is carried out using proposed SSA design. In this method 99.4% overall computational accuracy for 16 bit addition even with 8 bit adder can be achieved.Introduction: In general power consumption and performance are critical parameters in the design of digital circuit. In digital signal processing the circuit is implemented for filtering, encryption or time to frequency or frequency to time domain transformations. Adders are the major building blocks in Arithmetic and logic unit (ALU). The normal adders are too slow or consume more energy than the performance of the design will be degraded. Approximate addition has been carried out as a means of achieving area, power and speed improvement. In this work an accuracy improvement static segment approximate technique is used based on the significance probability by negating lower order bytes of input information to achieve the required computational accuracy for human perception interfaced applications is proposed. The proposed design is incorporated with spatial domain image enhancement technique, which operates directly on pixels and gives a quantitative measure for human perception. Existing System The Existing system consists of full adder which consumes more energy, area, power etc. The image processing application using adders used in wide range of application like image encryption, image mixing, image compressing etc. Full adders are used in this process which consumes less power, too fast, less area and more energy efficient. The traditional ripple carry adder is therefore no longer suitable for large adders because of its low speed performance. Many different types of fast adders, such as the carry skip adder, carry select adder and carry look ahead adder have been developed.Proposed system This project proposes a design of high speed energy efficient static segment adder which improves the overall performance based on static segmentation. Accuracy Adjustment logic is incorporated to improve the accuracy derived from negating lower order bytes of input operands. To achieve computational Accuracy for error tolerant applications an integration of static segmentation method and Accuracy Adjustment logic is used. The proposed adder design enables to provide high speed and energy efficient through the static segmentation method.